1. Field
Aspects of the present disclosure relate generally to memory interfaces, and more particularly, to synchronization systems and methods for memory interfaces.
2. Background
A system on a chip (SoC) may include a memory interface for interfacing one or more blocks (e.g., CPU, GPU, etc.) on the SoC with an external memory device. The memory interface may comprise a centrally-located memory controller, and a plurality of physical (PHY) blocks located along the periphery of the SoC. The memory controller manages the flow of data between the external memory device and blocks on the SoC that need to access the external memory device. When a block on the SoC needs to write data to the memory external device, the memory controller sends the data to one or more of the PHY blocks along with a clock signal and a command/address (CA) signal. The one or more PHY blocks condition the data, the clock signal and the CA signal for output to the external memory device in accordance with an applicable memory standard.